* Ingo Molnar <[email protected]> wrote:
> > --- a/arch/x86/boot/compressed/head_64.S
> > +++ b/arch/x86/boot/compressed/head_64.S
> > @@ -315,6 +315,18 @@ ENTRY(startup_64)
> > * The first step is go into compatibility mode.
> > */
> >
> > + /*
> > + * Find suitable place for trampoline and populate it.
> > + * The address will be stored in RCX.
> > + *
> > + * RSI holds real mode data and need to be preserved across
> > + * a function call.
> > + */
> > + pushq %rsi
> > + call place_trampoline
> > + popq %rsi
> > + movq %rax, %rcx
> > +
> > /* Clear additional page table */
> > leaq lvl5_pgtable(%rbx), %rdi
> > xorq %rax, %rax
>
> One request: it's always going to be fragile if the _only_ thing that uses
> the
> trampoline is the 5-level paging code.
>
> Could we use the trampoline in the 4-level paging case too? It's not
> required, but
> would test much of the trampoline allocation and copying machinery - and the
> performance cost is negligible.
Note that right now the trampoline is pointless on 4-level setups, so there's
nothing to copy - but we could perhaps make it meaningful. But maybe it's not a
good idea.
One other detail I noticed:
/* Bound size of trampoline code */
.org lvl5_trampoline_src + LVL5_TRAMPOLINE_CODE_SIZE
will this generate a build error if the trampoline code exceeds 0x40?
Thanks,
Ingo
