RISC-V doesn't currently specify a mechanism for enabling or disabling CPUs. Instead, we assume that all CPUs are enabled on boot, and if someone wants to save power we instead put a CPU to sleep via a WFI loop.
This patch adds "enable-method" to the RISC-V CPU binding, which currently only has the value "none". This allows us to change the enable method in the future. CC: Mark Rutland <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]> --- Documentation/devicetree/bindings/riscv/cpus.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af5dc3..dd9e1ae197e2 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -82,6 +82,11 @@ described below. Value type: <string> Definition: Contains the RISC-V ISA string of this hart. These ISA strings are defined by the RISC-V ISA manual. + - cpu-enable-method: + Usage: required + Value type: <stringlist> + Definition: Must be one of + "none": This CPU's state cannot be changed. Example: SiFive Freedom U540G Development Kit --------------------------------------------- @@ -105,6 +110,7 @@ Linux is allowed to run on. reg = <0>; riscv,isa = "rv64imac"; status = "disabled"; + enable-method = "none"; L10: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -130,6 +136,7 @@ Linux is allowed to run on. reg = <1>; riscv,isa = "rv64imafdc"; status = "okay"; + enable-method = "none"; tlb-split; L13: interrupt-controller { #interrupt-cells = <1>; -- 2.13.6
