On Mon, Nov 20, 2017 at 06:20:39PM +0000, Ard Biesheuvel wrote: > On 20 November 2017 at 18:06, Will Deacon <will.dea...@arm.com> wrote: > > I'll see if I can measure the cost of the current vbar switching to get > > an idea of the potential performance available. > > > > Yeah, makes sense. If the bulk of the performance hit is elsewhere, > there's no point in focusing on this bit.
I had a go at implementing a variant on your suggestion where we avoid swizzling the vbar on exception entry/exit but I couldn't reliably measure a difference in performance. It appears that the ISB needed by the TTBR change is dominant, so the vbar write is insignificant. Will