On 11/27/2017 1:16 PM, Alan Stern wrote:
> This is essentially a repeat of an email I sent out before the
> Thanksgiving holiday, the assumption being that lack of any responses
> was caused by the holiday break. (And this time the message is CC'ed
> to LKML, so there will be a public record of it.)
>
> A few people have said they believe the Linux Kernel Memory Model
> should make unlock followed by lock (of the same variable) act as a
> write memory barrier. In other words, they want the memory model to
> forbid the following litmus test:
>
<snip>
>
> I (and others!) would like to know people's opinions on these matters.
>
> Alan Stern
While we're here, let me ask about another test which isn't directly
about unlock/lock but which is still somewhat related to this
discussion:
"MP+wmb+xchg-acq" (or some such)
{}
P0(int *x, int *y)
{
WRITE_ONCE(*x, 1);
smp_wmb();
WRITE_ONCE(*y, 1);
}
P1(int *x, int *y)
{
r1 = atomic_xchg_relaxed(y, 2);
r2 = smp_load_acquire(y);
r3 = READ_ONCE(*x);
}
exists (1:r1=1 /\ 1:r2=2 /\ 1:r3=0)
C/C++ would call the atomic_xchg_relaxed part of a release sequence
and hence would forbid this outcome.
x86 and Power would forbid this. ARM forbids this via a special-case
rule in the memory model, ordering atomics with later load-acquires.
RISC-V, however, wouldn't forbid this by default using RCpc or RCsc
atomics for smp_load_acquire(). It's an "fri; rfi" type of pattern,
because xchg doesn't have an inherent internal data dependency.
If the Linux memory model is going to forbid this outcome, then
RISC-V would either need to use fences instead, or maybe we'd need to
add a special rule to our memory model similarly. This is one detail
where RISC-V is still actively deciding what to do.
Have you all thought about this test before? Any idea which way you
are leaning regarding the outcome above?
Thanks,
Dan
