Add binding documentation for the Microsemi Ocelot reset block.
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: Sebastian Reichel <[email protected]>
Cc: [email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
new file mode 100644
index 000000000000..1bcf276b04cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -0,0 +1,17 @@
+Microsemi Ocelot reset controller
+
+The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
+SoC MIPS core.
+
+Required Properties:
+ - compatible: "mscc,ocelot-chip-reset"
+
+Example:
+ syscon@71070000 {
+ compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+ reg = <0x71070000 0x1c>;
+
+ reset {
+ compatible = "mscc,ocelot-chip-reset";
+ };
+ };
--
2.15.1
