On 12/09/2017 05:59 AM, Eugeniy Paltsev wrote:
Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.
It will be applied at the core pll driver probing.
Eugeniy Paltsev (4):
ARC: [plat-hsdk]: Set initial core pll output frequency
ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
ARC: [plat-axs103]: Set initial core pll output frequency
ARC: [plat-axs103] refactor the quad core DT quirk code
arch/arc/boot/dts/axc003.dtsi | 3 +++
arch/arc/boot/dts/axc003_idu.dtsi | 3 +++
arch/arc/boot/dts/hsdk.dts | 3 +++
arch/arc/plat-axs10x/axs10x.c | 18 ++++++++---------
arch/arc/plat-hsdk/platform.c | 42 ---------------------------------------
5 files changed, 17 insertions(+), 52 deletions(-)
Alexey can you give this a quick spin on either boards and confirm if the DT
changes are indeed what they were before ?
Thx,
-Vineet
