For Intel the manuals state that it's 16 entries -- 2.5.2.1 Agner also reports 16 (presumably experimentally measured) e.g. http://www.agner.org/optimize/microarchitecture.pdf [3.8] For AMD it can be larger, for example 32 entries on Fam17h (but 16 entries on Fam16h).
For future proofing a binary, or a new AMD processor, 32 calls are required. I would suggest tuning this based on the current CPU (which also covers the future case while saving cycles now) to save overhead. On Mon, Jan 8, 2018 at 3:16 AM, Andrew Cooper <andrew.coop...@citrix.com> wrote: > On 08/01/18 10:42, Paul Turner wrote: >> A sequence for efficiently refilling the RSB is: >> mov $8, %rax; >> .align 16; >> 3: call 4f; >> 3p: pause; call 3p; >> .align 16; >> 4: call 5f; >> 4p: pause; call 4p; >> .align 16; >> 5: dec %rax; >> jnz 3b; >> add $(16*8), %rsp; >> This implementation uses 8 loops, with 2 calls per iteration. This is >> marginally faster than a single call per iteration. We did not >> observe useful benefit (particularly relative to text size) from >> further unrolling. This may also be usefully split into smaller (e.g. >> 4 or 8 call) segments where we can usefully pipeline/intermix with >> other operations. It includes retpoline type traps so that if an >> entry is consumed, it cannot lead to controlled speculation. On my >> test system it took ~43 cycles on average. Note that non-zero >> displacement calls should be used as these may be optimized to not >> interact with the RSB due to their use in fetching RIP for 32-bit >> relocations. > > Guidance from both Intel and AMD still states that 32 calls are required > in general. Is your above code optimised for a specific processor which > you know the RSB to be smaller on? > > ~Andrew
