On Monday 08 January 2018 07:47 AM, David Lechner wrote:
> This adds platform-specific declarations for the PLL clocks on TI
> DaVinci 644x based systems.
DM644x
> Signed-off-by: David Lechner <da...@lechnology.com>
> + * Copyright (C) 2017 David Lechner <da...@lechnology.com>
2018 now.
> +void __init dm644x_pll_clk_init(void __iomem *pll1, void __iomem *pll2)
> +{
> + const struct davinci_pll_divclk_info *info;
> +
> + davinci_pll_clk_register("pll1", "ref_clk", pll1);
> + for (info = dm644x_pll1_divclk_info; info->name; info++)
> + davinci_pll_divclk_register(info, pll1);
> + davinci_pll_aux_clk_register("pll1_aux_clk", "ref_clk", pll1);
> + davinci_pll_bpdiv_clk_register("pll1_sysclkbp", "ref_clk", pll1);
> +
> + davinci_pll_clk_register("pll2", "ref_clk", pll2);
> + for (info = dm644x_pll2_divclk_info; info->name; info++)
> + davinci_pll_divclk_register(info, pll2);
> + davinci_pll_bpdiv_clk_register("pll2_sysclkbp", "ref_clk", pll2);
> +}
Here too, more line spacing will help.
With those minor comments.
Reviewed-by: Sekhar Nori <nsek...@ti.com>
Thanks,
Sekhar
