[PATCH 13/16] arm64: Add support for checking errata based on a list of MIDRS

[Suzuki K Poulose]

Add helpers for detecting an errata on list of midr ranges
of affected CPUs.

Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com>
---
 arch/arm64/include/asm/cpufeature.h |  1 +
 arch/arm64/kernel/cpu_errata.c      | 40 ++++++++++++++++++++++---------------
 2 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h 
b/arch/arm64/include/asm/cpufeature.h
index a3d54c2c411f..70712de687c7 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -136,6 +136,7 @@ struct arm64_cpu_capabilities {
        int (*enable)(const struct arm64_cpu_capabilities *caps);
        union {
                struct midr_range midr_range;   /* To be used for erratum 
handling only */
+               const struct midr_range *midr_range_list;
                struct {        /* Feature register checking */
                        u32 sys_reg;
                        u8 field_pos;
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 10eb7fa0d0d7..8472d156c225 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -29,6 +29,13 @@ is_affected_midr_range(const struct arm64_cpu_capabilities 
*entry, int scope)
 }
 
 static bool __maybe_unused
+is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, int 
scope)
+{
+       WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
+       return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
+}
+
+static bool __maybe_unused
 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
 {
        u32 model;
@@ -196,6 +203,22 @@ static int qcom_enable_link_stack_sanitization(
        .matches = is_affected_midr_range, \
        .midr_range = MIDR_ALL_VERSIONS(model)
 
+/* Errata affecting a list of midr ranges, with same work around */
+#define ERRATA_MIDR_RANGE_LIST(midr_list) \
+       .type = ARM64_CPUCAP_STRICT_CPU_LOCAL_ERRATUM, \
+       .matches = is_affected_midr_range_list, \
+       .midr_range_list = midr_list
+
+#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
+static const struct midr_range cortex_bp_harden_cpus[] = {
+       MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
+       MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
+       MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
+       MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
+       {},
+};
+#endif
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #if    defined(CONFIG_ARM64_ERRATUM_826319) || \
        defined(CONFIG_ARM64_ERRATUM_827319) || \
@@ -330,22 +353,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
        {
                .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
-               ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
-               .enable = enable_psci_bp_hardening,
-       },
-       {
-               .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
-               ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
-               .enable = enable_psci_bp_hardening,
-       },
-       {
-               .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
-               ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
-               .enable = enable_psci_bp_hardening,
-       },
-       {
-               .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
-               ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
+               ERRATA_MIDR_RANGE_LIST(cortex_bp_harden_cpus),
                .enable = enable_psci_bp_hardening,
        },
        {
-- 
2.13.6