----- On Feb 6, 2018, at 11:51 AM, efficios [email protected] wrote:
> Ensure we gather architecture requirements about each architecture supporting > the "sync_core" membarrier command in a single file under > Documentation/features. > > [ This patch applies on top of tip sched/core. ] please disregard this email. I will fix my git config on this dev machine and re-send. Thanks, Mathieu > > Signed-off-by: Mathieu Desnoyers <[email protected]> > Cc: Ingo Molnar <[email protected]> > Cc: Thomas Gleixner <[email protected]> > Cc: Peter Zijlstra (Intel) <[email protected]> > Cc: Andrea Parri <[email protected]> > Cc: Andrew Hunter <[email protected]> > Cc: Andy Lutomirski <[email protected]> > Cc: Avi Kivity <[email protected]> > Cc: Benjamin Herrenschmidt <[email protected]> > Cc: Boqun Feng <[email protected]> > Cc: Dave Watson <[email protected]> > Cc: David Sehr <[email protected]> > Cc: Greg Hackmann <[email protected]> > Cc: H. Peter Anvin <[email protected]> > Cc: Linus Torvalds <[email protected]> > Cc: Maged Michael <[email protected]> > Cc: Michael Ellerman <[email protected]> > Cc: Paul E. McKenney <[email protected]> > Cc: Paul Mackerras <[email protected]> > Cc: Russell King <[email protected]> > Cc: Will Deacon <[email protected]> > Cc: [email protected] > Cc: [email protected] > --- > .../sched/membarrier-sync-core/arch-support.txt | 62 ++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 > Documentation/features/sched/membarrier-sync-core/arch-support.txt > > diff --git > a/Documentation/features/sched/membarrier-sync-core/arch-support.txt > b/Documentation/features/sched/membarrier-sync-core/arch-support.txt > new file mode 100644 > index 0000000..2c815a7 > --- /dev/null > +++ b/Documentation/features/sched/membarrier-sync-core/arch-support.txt > @@ -0,0 +1,62 @@ > +# > +# Feature name: membarrier-sync-core > +# Kconfig: ARCH_HAS_MEMBARRIER_SYNC_CORE > +# description: arch supports core serializing membarrier > +# > +# Architecture requirements > +# > +# * arm64 > +# > +# Rely on eret context synchronization when returning from IPI handler, and > +# when returning to user-space. > +# > +# * x86 > +# > +# x86-32 uses IRET as return from interrupt, which takes care of the IPI. > +# However, it uses both IRET and SYSEXIT to go back to user-space. The IRET > +# instruction is core serializing, but not SYSEXIT. > +# > +# x86-64 uses IRET as return from interrupt, which takes care of the IPI. > +# However, it can return to user-space through either SYSRETL (compat code), > +# SYSRETQ, or IRET. > +# > +# Given that neither SYSRET{L,Q}, nor SYSEXIT, are core serializing, we rely > +# instead on write_cr3() performed by switch_mm() to provide core > serialization > +# after changing the current mm, and deal with the special case of kthread -> > +# uthread (temporarily keeping current mm into active_mm) by issuing a > +# sync_core_before_usermode() in that specific case. > +# > + ----------------------- > + | arch |status| > + ----------------------- > + | alpha: | TODO | > + | arc: | TODO | > + | arm: | TODO | > + | arm64: | ok | > + | blackfin: | TODO | > + | c6x: | TODO | > + | cris: | TODO | > + | frv: | TODO | > + | h8300: | TODO | > + | hexagon: | TODO | > + | ia64: | TODO | > + | m32r: | TODO | > + | m68k: | TODO | > + | metag: | TODO | > + | microblaze: | TODO | > + | mips: | TODO | > + | mn10300: | TODO | > + | nios2: | TODO | > + | openrisc: | TODO | > + | parisc: | TODO | > + | powerpc: | TODO | > + | s390: | TODO | > + | score: | TODO | > + | sh: | TODO | > + | sparc: | TODO | > + | tile: | TODO | > + | um: | TODO | > + | unicore32: | TODO | > + | x86: | ok | > + | xtensa: | TODO | > + ----------------------- > -- > 1.9.1 -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com
