On Wed, Feb 07, 2018 at 11:43:37AM -0800, Linus Torvalds wrote: > We could just also decide that the only thing that the modrm bytes of > UD0 actually *affect* is how the CPU might act for a page-crossing > instruction. > > Because I think that's the only semantic difference: if it's a > page-crosser, the instruction could take a page fault before raising > the #UD. > > Is there any other decode issue we might want to look out for?
Yes, AMD doesn't do UD0 with a ModRM: "UD0 0F FF Raise an invalid opcode exception" And I don't know about the other x86 vendors; what fun they've had with the UD*. I guess we should make sure the following bytes are a valid insn. Btw Rudolf had experimented with this, CCed, and he showed that on Intel you get a SIGSEGV for a page crosser with UD1 and SIGILL on AMD. I guess you can get the same with UD0 apparently. > Anyway, then we'd make the rule be: > > - we promise to always pad up the following bytes (our extra warning > information etc) so that we never have a missing page afterwards (this > is presumably practically speaking already the case). It might still > be a page-crossing instruction, but we won't take a page fault in > kernel space (due to it being at the end of some text sectoin or > whatever that changes the NX bit or due to DEBUG_PAGEALLOC having > unmapped the next page). Yeah, I guess we can control the bytes there. > - we special-case the decoder so that we don't get this warning That's easy - the decoder should simply say to upgrade objdump. > and then we just ignore the issue entirely. > > Hmm? Sounds like a plan but with those things the devil's in the detail. Nothing sounds too nasty now, though. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.