On Tue, Jan 09, 2018 at 07:04:01PM +0000, Suzuki K Poulose wrote:
> So far we have only supported 3 level page table with fixed IPA of 40bits.
> Fix stage2_flush_memslot() to accommodate for 4 level tables.
> 

Acked-by: Christoffer Dall <christoffer.d...@linaro.org>

> Cc: Marc Zyngier <marc.zyng...@arm.com>
> Cc: Christoffer Dall <cd...@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com>
> ---
>  virt/kvm/arm/mmu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
> index 761787befd3b..e6548c85c495 100644
> --- a/virt/kvm/arm/mmu.c
> +++ b/virt/kvm/arm/mmu.c
> @@ -375,7 +375,8 @@ static void stage2_flush_memslot(struct kvm *kvm,
>       pgd = kvm->arch.pgd + stage2_pgd_index(addr);
>       do {
>               next = stage2_pgd_addr_end(addr, end);
> -             stage2_flush_puds(kvm, pgd, addr, next);
> +             if (!stage2_pgd_none(*pgd))
> +                     stage2_flush_puds(kvm, pgd, addr, next);
>       } while (pgd++, addr = next, addr != end);
>  }
>  
> -- 
> 2.13.6
> 

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