4.9-stable review patch. If anyone has any objections, please let me know.
------------------ From: David Woodhouse <d...@amazon.co.uk> (cherry picked from commit fc67dd70adb711a45d2ef34e12d1a8be75edde61) Add three feature bits exposed by new microcode on Intel CPUs for speculation control. Signed-off-by: David Woodhouse <d...@amazon.co.uk> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Reviewed-by: Greg Kroah-Hartman <gre...@linuxfoundation.org> Reviewed-by: Borislav Petkov <b...@suse.de> Cc: gno...@lxorguk.ukuu.org.uk Cc: a...@linux.intel.com Cc: ashok....@intel.com Cc: dave.han...@intel.com Cc: karah...@amazon.de Cc: ar...@linux.intel.com Cc: torva...@linux-foundation.org Cc: pet...@infradead.org Cc: b...@alien8.de Cc: pbonz...@redhat.com Cc: tim.c.c...@linux.intel.com Cc: gre...@linux-foundation.org Link: https://lkml.kernel.org/r/1516896855-7642-3-git-send-email-d...@amazon.co.uk Signed-off-by: David Woodhouse <d...@amazon.co.uk> Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org> --- arch/x86/include/asm/cpufeatures.h | 3 +++ 1 file changed, 3 insertions(+) --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -296,6 +296,9 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ +#define X86_FEATURE_SPEC_CTRL (18*32+26) /* Speculation Control (IBRS + IBPB) */ +#define X86_FEATURE_STIBP (18*32+27) /* Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ /* * BUG word(s)
