On Tue, 2018-02-13 at 10:21 +0000, David Woodhouse wrote: > > > So the right logic is: > > > > - if the VM has IBRS_ALL, pass through the MSR when it is zero and > > intercept writes when it is one (no writes should happen) > > > > - if the VM doesn't have IBRS_ALL, do as we are doing now, independent > > of what the host spectre_v2_ibrs_all() setting is. > > We end up having to turn IBRS on again on vmexit then, taking care that > no conditional branch can go round it. So that becomes an > *unconditional* wrmsr or lfence in the vmexit path. We really don't > want that.
Note that being able to keep it simple in KVM was basically what made the difference between me tolerating IBRS_ALL as Intel currently define it, and throwing my toys out of the pram (as I had done in the first iterations of this patch). If we *can't* keep it nice and simple in KVM, then I think we *really* want Intel to make the hardware bit a no-op. If not for all CPUs with the IBRS_ALL bit, then for all *future* CPUs and they can define a new IBRS_ALL_UNCONDITIONAL bit. Which is the only one we'd ever care about.
Description: S/MIME cryptographic signature