On 08/02/2018 23:58, Tom Lendacky wrote:
> Create an entry in the new MSR as a feature framework to allow a guest to
> recognize LFENCE as a serializing instruction on AMD processors.  The MSR
> can only be set by the host, any write by the guest will be ignored.  A
> read by the guest will return the value as set by the host.  In this way,
> the support to expose the feature to the guest is controlled by the
> hypervisor.
> 
> Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com>
> ---
>  arch/x86/kvm/svm.c |   16 ++++++++++++++++
>  arch/x86/kvm/x86.c |    6 ++++++
>  2 files changed, 22 insertions(+)
> 
> @@ -4047,6 +4052,17 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct 
> msr_data *msr)
>       case MSR_VM_IGNNE:
>               vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", 
> ecx, data);
>               break;
> +     case MSR_F10H_DECFG:
> +             /* Only the host can set this MSR, silently ignore */
> +             if (!msr->host_initiated)
> +                     break;

Just one thing I'm wondering, should we #GP if the guest attempts to
clear MSR_F10H_DECFG_LFENCE_SERIALIZE?

Thanks,

Paolo

> +
> +             /* Check the supported bits */
> +             if (!kvm_valid_msr_feature(MSR_F10H_DECFG, data))
> +                     return 1;
> +
> +             svm->msr_decfg = data;
> +             break;
>       case MSR_IA32_APICBASE:
>               if (kvm_vcpu_apicv_active(vcpu))
>                       avic_update_vapic_bar(to_svm(vcpu), data);
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 4251c34..21ec73b 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -1060,7 +1060,13 @@ struct kvm_msr_based_features {
>       u64 value;                      /* MSR value */
>  };
>  
> +static const struct x86_cpu_id msr_decfg_match[] = {
> +     { X86_VENDOR_AMD, X86_FAMILY_ANY, X86_MODEL_ANY, 
> X86_FEATURE_LFENCE_RDTSC },
> +     {}
> +};
> +
>  static struct kvm_msr_based_features msr_based_features[] = {
> +     { MSR_F10H_DECFG, MSR_F10H_DECFG_LFENCE_SERIALIZE, msr_decfg_match },
>       {}
>  };
>  
> 

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