This changeset applies on top of the previous updates series
available here [0].

Most of the changes proposed here are related to the plls of meson
SoCs. Details can be found in each patches but, in nutshell, there
is :
* a bit of clean-up,
* improved pll capabilities using the frac parameter,
* several clocks added to model the tree more accurately.

Beware: patch #10 depends on this core clock framework fix: [1]
As explained in the description on the patch, if the gates are
added w/o this fix, the system will crash when
clk_disable_unused() is called.


Jerome Brunet (11):
  clk: meson: add fractional part of meson8b fixed_pll
  clk: meson: poke pll CNTL last
  clk: meson: remove special gp0 lock loop
  clk: meson: improve pll driver results with frac
  clk: meson: add gp0 frac parameter for axg and gxl
  clk: meson: add ROUND_CLOSEST to the pll driver
  clk: meson: axg: add hifi clock bindings
  clk: meson: axg: add hifi pll clock
  clk: meson: add mpll pre-divider
  clk: meson: add fdiv clock gates
  clk: meson: clean-up clk81 clocks

 drivers/clk/meson/axg.c              | 184 +++++++++++++++++++++++++++++++----
 drivers/clk/meson/axg.h              |   8 +-
 drivers/clk/meson/clk-pll.c          | 154 ++++++++++++++++++-----------
 drivers/clk/meson/clkc.h             |  15 +--
 drivers/clk/meson/gxbb.c             | 141 +++++++++++++++++++++++----
 drivers/clk/meson/gxbb.h             |  10 +-
 drivers/clk/meson/meson8b.c          | 128 ++++++++++++++++++++----
 drivers/clk/meson/meson8b.h          |   8 +-
 include/dt-bindings/clock/axg-clkc.h |   1 +
 9 files changed, 521 insertions(+), 128 deletions(-)


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