On Tue, Mar 06, 2018 at 08:27:33PM +0800, Aaron Lu wrote:
> On Tue, Mar 06, 2018 at 08:55:57AM +0100, Vlastimil Babka wrote:
> > So the adjacent line prefetch might be disabled? Could you check bios or
> > the MSR mentioned in
> > https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors
> root@lkp-bdw-ep2 ~# rdmsr 0x1a4
Technically 0x1a4 is per-core, so you should run rdmsr -a 0x1a4 in order to
check all the cores. But I can't imagine they're being set differently on
> > instructions (calculated from itlb misses and insns-per-itlb-miss) shows
> > less than 1% increase, so dunno. And the improvement comes from reduced
> > dTLB-load-misses? That makes no sense for order-0 buddy struct pages
> > which always share a page. And the memmap mapping should use huge pages.
> THP is disabled to stress order 0 pages(should have mentioned this in
> patch's description, sorry about this).
THP isn't related to memmap; the kernel uses huge pages (usually the 1G
pages) in order to map its own memory.