The ssi1_ipg clock depends on ssi1_ipg_per. Set ssi1_ipg_per as parent
clock of ssi1_ipg. Without this link, the fsl_ssi driver does not
activate the ssi1_ipg clock correctly and ssi1 is unable to transfer
audio data.
Fix the parent clock of ssi2 as well, it shows the same behaviour.
Signed-off-by: Martin Kaiser <mar...@kaiser.cx>
---
Dear all,
could you have a look at this patch? This makes SSI1 and 2 work for me.
With the default "ipg" parent clocks, I get no ipg clocks on the SSIs.
However, I was wondering why we don't need anything similar e.g. for the
UARTs...
Best regards,
Martin
drivers/clk/imx/clk-imx25.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c
index 23686f7..ee2852f 100644
--- a/drivers/clk/imx/clk-imx25.c
+++ b/drivers/clk/imx/clk-imx25.c
@@ -217,8 +217,8 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base)
clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2), 8);
clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2), 9);
clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2), 10);
- clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
- clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
+ clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ssi1_ipg_per",
ccm(CCM_CGCR2), 11);
+ clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ssi2_ipg_per",
ccm(CCM_CGCR2), 12);
clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14);
clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15);
--
2.1.4
