From: yangbo lu <yangbo...@nxp.com>

[ Upstream commit a627f025eb0534052ff451427c16750b3530634c ]

The ls1046a datasheet specified that the max SD clock frequency
for eSDHC SDR104/HS200 was 167MHz, and the ls1012a datasheet
specified it's 125MHz for ls1012a. So this patch is to add the
limitation.

Signed-off-by: Yangbo Lu <yangbo...@nxp.com>
Acked-by: Adrian Hunter <adrian.hun...@intel.com>
Signed-off-by: Ulf Hansson <ulf.hans...@linaro.org>
Signed-off-by: Sasha Levin <alexander.le...@microsoft.com>
---
 drivers/mmc/host/sdhci-of-esdhc.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-esdhc.c 
b/drivers/mmc/host/sdhci-of-esdhc.c
index 83b1226471c1..ac66c61d9433 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -418,6 +418,20 @@ static void esdhc_of_set_clock(struct sdhci_host *host, 
unsigned int clock)
        if (esdhc->vendor_ver < VENDOR_V_23)
                pre_div = 2;
 
+       /*
+        * Limit SD clock to 167MHz for ls1046a according to its datasheet
+        */
+       if (clock > 167000000 &&
+           of_find_compatible_node(NULL, NULL, "fsl,ls1046a-esdhc"))
+               clock = 167000000;
+
+       /*
+        * Limit SD clock to 125MHz for ls1012a according to its datasheet
+        */
+       if (clock > 125000000 &&
+           of_find_compatible_node(NULL, NULL, "fsl,ls1012a-esdhc"))
+               clock = 125000000;
+
        /* Workaround to reduce the clock frequency for p1010 esdhc */
        if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
                if (clock > 20000000)
-- 
2.14.1

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