Thanks for fixing it. Patch looks good to me. +Alex to pull this patch. Reviewed by: Kirti Wankhede <kwankh...@nvidia.com>
Thanks, Kirti On 3/8/2018 12:38 PM, Shunyong Yang wrote: > When FIFO mode is enabled, the receive data available interrupt > (UART_IIR_RDI in code) should be triggered when the number of data > in FIFO is equal or larger than interrupt trigger level. > > This patch changes the trigger level check to ensure multiple bytes > received from upper layer can trigger RDI interrupt correctly. > > Cc: Joey Zheng <yu.zh...@hxt-semitech.com> > Signed-off-by: Shunyong Yang <shunyong.y...@hxt-semitech.com> > --- > samples/vfio-mdev/mtty.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/samples/vfio-mdev/mtty.c b/samples/vfio-mdev/mtty.c > index 09f255bdf3ac..7abb79d8313d 100644 > --- a/samples/vfio-mdev/mtty.c > +++ b/samples/vfio-mdev/mtty.c > @@ -534,7 +534,7 @@ static void handle_bar_read(unsigned int index, struct > mdev_state *mdev_state, > > /* Interrupt priority 2: Fifo trigger level reached */ > if ((ier & UART_IER_RDI) && > - (mdev_state->s[index].rxtx.count == > + (mdev_state->s[index].rxtx.count >= > mdev_state->s[index].intr_trigger_level)) > *buf |= UART_IIR_RDI; > >
