3.16.56-rc1 review patch.  If anyone has any objections, please let me know.


From: Tom Lendacky <thomas.lenda...@amd.com>

commit e4d0e84e490790798691aaa0f2e598637f1867ec upstream.

To aid in speculation control, make LFENCE a serializing instruction
since it has less overhead than MFENCE.  This is done by setting bit 1
of MSR 0xc0011029 (DE_CFG).  Some families that support LFENCE do not
have this MSR.  For these families, the LFENCE instruction is already

Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com>
Signed-off-by: Thomas Gleixner <t...@linutronix.de>
Reviewed-by: Reviewed-by: Borislav Petkov <b...@suse.de>
Cc: Peter Zijlstra <pet...@infradead.org>
Cc: Tim Chen <tim.c.c...@linux.intel.com>
Cc: Dave Hansen <dave.han...@intel.com>
Cc: Borislav Petkov <b...@alien8.de>
Cc: Dan Williams <dan.j.willi...@intel.com>
Cc: Linus Torvalds <torva...@linux-foundation.org>
Cc: Greg Kroah-Hartman <gre...@linux-foundation.org>
Cc: David Woodhouse <d...@amazon.co.uk>
Cc: Paul Turner <p...@google.com>
[bwh: Backported to 3.16: adjust filename, context]
Signed-off-by: Ben Hutchings <b...@decadent.org.uk>
 arch/x86/include/uapi/asm/msr-index.h |  2 ++
 arch/x86/kernel/cpu/amd.c             | 10 ++++++++++
 2 files changed, 12 insertions(+)

--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -223,6 +223,8 @@
 #define FAM10H_MMIO_CONF_BASE_MASK     0xfffffffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT    20
 #define MSR_FAM10H_NODE_ID             0xc001100c
+#define MSR_F10H_DECFG                 0xc0011029
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1                        0xc001001a
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -673,6 +673,16 @@ static void init_amd(struct cpuinfo_x86
                set_cpu_cap(c, X86_FEATURE_K8);
        if (cpu_has_xmm2) {
+               /*
+                * A serializing LFENCE has less overhead than MFENCE, so
+                * use it for execution serialization.  On families which
+                * don't have that MSR, LFENCE is already serializing.
+                * msr_set_bit() uses the safe accessors, too, even if the MSR
+                * is not present.
+                */
+               msr_set_bit(MSR_F10H_DECFG,
+                           MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
                /* MFENCE stops RDTSC speculation */
                set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);

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