On Sun, Mar 11, 2018 at 11:29 PM, Wu Hao <hao...@intel.com> wrote:
> On Sun, Mar 11, 2018 at 01:09:31PM -0700, matthew.gerl...@linux.intel.com
>> Hi Hao,
>> I do think we should consider different hw implementations with this code
>> because it does look like most of it is generic. Specifically, I think
>> we should consider DFH based fpga images that have been shipped already,
>> and I think we need to consider new hardware implementations as well.
>> Full disclosure, I am particularly interested in porting to a new hw
>> implementation for partial reconfiguration.
The manager may not be the only thing that has to change for a new
implementation, i.e. will your 'port' be able to work with this
patchset? In the current implementation, the port is part of the dfl
enumeration code (dfl.c and dfl.h) rather than being part of the
bridge for some reason. We discussed the possibility of putting the
port enable/disable code into the bridge driver , but that didn't
seem feasible at least last December. I still would feel more
confident if port were part of the bridge instead of part of dfl.