> On Mon, Mar 19, 2018 at 10:47:46PM -0400, Sinan Kaya wrote: > > Code includes wmb() followed by writel(). writel() already has a barrier on > > some architectures like arm64. > > > > This ends up CPU observing two barriers back to back before executing > the > > register write. > > > > Since code already has an explicit barrier call, changing writel() to > > writel_relaxed(). > > > > Signed-off-by: Sinan Kaya <[email protected]> > > drivers/infiniband/hw/cxgb4/t4.h | 14 +++++++------- > > 1 file changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/infiniband/hw/cxgb4/t4.h > b/drivers/infiniband/hw/cxgb4/t4.h > > index 8369c7c..6e5658a 100644 > > +++ b/drivers/infiniband/hw/cxgb4/t4.h > > @@ -457,7 +457,7 @@ static inline void pio_copy(u64 __iomem *dst, u64 > *src) > > int count = 8; > > > > while (count) { > > - writeq(*src, dst); > > + writeq_relaxed(*src, dst); > > src++; > > dst++; > > count--; > > This is another case where writes can be re-ordered.. IIRC dst is WC > BAR memory, so the NIC should tolerate re-ordering, but Steve will > have to ack this. >
Yes, this is WC BAR memory. The goal is that pio_copy() will enable write-combining this into a single 64B pci-e transaction.
