[PATCH v4 19/22] iommu/intel-svm: do not flush iotlb for viommu

[Jacob Pan]

vIOMMU passdown invalidation will be inclusive, PASID cache invalidation
includes TLBs. See Intel VT-d Specification Ch 6.5.2.2 for details.

Signed-off-by: Jacob Pan <jacob.jun....@linux.intel.com>
---
 drivers/iommu/intel-svm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index 3a7bc77..66b8e10 100644
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -284,7 +284,9 @@ static void intel_mm_release(struct mmu_notifier *mn, 
struct mm_struct *mm)
        rcu_read_lock();
        list_for_each_entry_rcu(sdev, &svm->devs, list) {
                intel_flush_pasid_dev(svm, sdev, svm->pasid);
-               intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
+               /* for emulated iommu, PASID cache invalidation implies 
IOTLB/DTLB */
+               if (!cap_caching_mode(svm->iommu->cap))
+                       intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, 
!svm->mm);
        }
        rcu_read_unlock();
 
-- 
2.7.4