On 4 April 2018 at 11:05, Masahiro Yamada <yamada.masah...@socionext.com> wrote:
> Hi.
>
> 2018-04-04 16:35 GMT+09:00 Ulf Hansson <ulf.hans...@linaro.org>:
>> On 27 March 2018 at 11:29, Masahiro Yamada
>> <yamada.masah...@socionext.com> wrote:
>>> Cadence sent out an errata report to their customers of this IP.
>>> This errata is not so severe, but the tune request should be sent
>>> twice to avoid the potential issue.
>>>
>>> Quote from the report:
>>>
>>> Problem Summary
>>> ---------------
>>> The IP6116 SD/eMMC PHY design has a timing issue on receive data path.
>>> This issue may lead to an incorrect values of read/write pointers of
>>> the synchronization FIFO. Such a situation can happen at the SDR104
>>> and HS200 tuning procedure when the PHY is requested to change a phase
>>> of sampling clock when moving to the next tuning iteration.
>>>
>>> Workarounds
>>> -----------
>>> The following are valid workarounds to resolve the issue:
>>>
>>> 1. In eMMC mode, software sends tune request twice instead of once at
>>>    each iteration. This means that the clock phase is not changed on
>>>    the second request so there is no potential for clock instability.
>>> 2. In SD mode, software must not use the hardware tuning and instead
>>>    perform an almost identical procedure to eMMC, using the HRS34 Tune
>>>    Force register.
>>>
>>> Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
>>
>> Do you want this to be tagged for stable as well? And perhaps you
>> could add a fixes tag?
>
>
> It would be nicer to make it a back-port candidate,
> but this patch can not cleanly apply to the initial commit of this driver.
>
>
> If you apply it for -next, it would be fine with me.

Okay, so I have queued it up for 4.18, thanks!

Kind regards
Uffe

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