Quoting Abel Vesa (2018-03-27 23:46:35) > From: Peter Chen <peter.c...@freescale.com> > > Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM > which is the output of USBOTG2 PHY. > > Signed-off-by: Peter Chen <peter.c...@freescale.com> > Signed-off-by: Irina Tirdea <irina.tir...@nxp.com> > Signed-off-by: Abel Vesa <abel.v...@nxp.com> > ---
Applied to clk-next
