On Wed, 11 Apr 2018 17:10:43 +0200 Peter Rosin <p...@axentia.se> wrote:
> On 2018-04-11 16:59, Boris Brezillon wrote: > > On Wed, 11 Apr 2018 16:44:10 +0200 > > Peter Rosin <p...@axentia.se> wrote: > > > >> Hi Nicolas, > >> > >> Boris asked for your input on this (the datasheet difference appears to > >> have no bearing on the issue) elsewhere in the tree of messages. It's > >> now been a week or so and I'm starting to wonder if you missed this > >> altogether or if you are simply out of office or something? > > > > I was wondering if you had given up on this problem, it seems you did > > not. > > I have my local patch to disable dma for the flash, but local patches > are always a disappointment. I understand that. > > > Did you try forcing the HLCDC to use the 2nd interface (ahb_id=1) > > instead of the first one? > > Just tried, and it's better that way, but the problem still exist and is > very visible on some (but apparently not all) flash accesses. Then your problems are unlikely to go away even with the priority adjustments because the DMAC do not use port 3, and priority stuff are only useful to enforce priority between masters accessing the same slave. I guess the real limitation comes the DRAM link, and asking the CPU to copy data from the NFC SRAM to the the DRAM is probably slowing things enough to let the HLCDC go through with its data transfers. Or maybe it has to do with the CPU data caches that are not immediately flushed to the DRAM when you copy things through the CPU.