On Thu, Apr 12, 2018 at 02:10:28PM +0200, Andreas Färber wrote:
> Am 12.04.2018 um 11:04 schrieb Linus Walleij:
> > On Wed, Apr 4, 2018 at 7:22 PM, Manivannan Sadhasivam
> > <manivannan.sadhasi...@linaro.org> wrote:
> >> Add pinctrl driver for Actions Semi S900 SoC. The driver supports
> >> pinctrl, pinmux and pinconf functionalities through a range of registers
> >> common to both gpio driver and pinctrl driver.
> >> Pinmux functionality is available only for the pin groups while the
> >> pinconf functionality is available for both pin groups and individual
> >> pins.
> >> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasi...@linaro.org>
> > Patch applied for v4.18
> > GOOD WORK!
> > We really need to get this in so that Andreas can work on S500
> > patches with this as a base.
> No, I refused to do that. If his patches get merged, Mani offered that
> he will take care of rebasing/rewriting S500 part.
Yes, if you don't have time then I can take this. Since you have already
sorted out the pin definitions, it will be much easier.
> > If any review comments still remain they can surely be addressed
> > with incremental improvement patches.
> My biggest problem was/is that Mani designed his structs totally
> different from mine, with no explanation why or how they correlate.
Agree. But we both worked orthogonally and please let me know if you
find anything wrong with my approach.
> Also I had protested against him defining fake pins for the drive
> strength. Since I did not have time to review the newer patches yet,
> please make sure that this is addressed _before_ merging. Changing the
> binding after the fact is a problem!
What do you mean by fake pins for drive strength? All the pins are named
after the group name given in the datasheet. And I have already mentioned
in the binding that we can only do group access for these pins. There is
_no_way_ you can individually configure drive strength for the pins, if you
do then the entire group will get configured, does this makes sense?
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