On Wed, Apr 11, 2018 at 07:06:36PM +0200, Paolo Bonzini wrote:
> On 11/04/2018 18:31, Peter Zijlstra wrote:
> >>> Prior Operation Subsequent Operation
> >>> --------------- ---------------------
> >>> R W RMW SV R W DR DW RMW SV
> >>> - - --- -- - - -- -- --- --
> >>> smp_store_mb() Y Y Y Y Y Y Y Y Y Y
> > I'm not sure about that, the generic version of that reads:
> >
> > include/asm-generic/barrier.h:#define __smp_store_mb(var, value)
> > do { WRITE_ONCE(var, value); __smp_mb(); } while (0)
> >
> > Which doesn't not have an smp_mb() before, so it doesn't actually order
> > prior; or I'm failing to read the table wrong.
>
> You're not, even better reason to document it. :) I was going from
> memory for the x86 version.
>
> I'll start tomorrow on fixes to the current document, while we discuss
> the split format and what to do about cumulativity and propagation.
> Besides, since smp_store_mb() is a store, so there is no DR or DW for the subsequent operations I think, because dependencies come from a read rather than a write. Regards, Boqun > Paolo
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