On Mon, Apr 16, 2018 at 12:35 PM, Stefan Agner <[email protected]> wrote:
> To reset the UART the SRST needs be cleared (low active). According
> to the documentation the bit will remain active for 4 module clocks
> until it is cleared (set to 1).
>
> Hence the real register need to be read in case the cached register
> indcates that the SRST bit is zero.
s/indcates/indicates
> This bug lead to wrong baudrate because the baud rate register got
> restored before reset completed in imx_flush_buffer.
>
> Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and
> UFCR")
> Signed-off-by: Stefan Agner <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
