Document new PWM device tree bindings for SiFive SoCs.
Signed-off-by: Wesley W. Terpstra <wes...@sifive.com>
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.../devicetree/bindings/pwm/pwm-sifive.txt | 28 ++++++++++++++++++++++
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create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
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+SiFive PWM controller
+
+Unlike most other PWM controllers, the SiFive PWM controller currently only
+supports one period for all channels in the PWM. This is set globally in DTS.
+The period also has significant restrictions on the values it can achieve,
+which the driver rounds to the nearest achievable frequency.
+
+Required properties:
+- compatible: should be "sifive,pwm0"
+- reg: physical base address and length of the controller's registers
+- clocks: The frequency the controller runs at
+- #pwm-cells: Should be 2.
+ The first cell is the PWM channel number
+ The second cell is the PWM polarity
+- sifive,approx-period: the driver will get as close to this period as it can
+- interrupts: one interrupt per PWM channel (currently unused in the driver)
+
+Examples:
+
+pwm: pwm@10020000 {
+ compatible = "sifive,pwm0";
+ reg = <0x0 0x10020000 0x0 0x1000>;
+ clocks = <&tlclk>;
+ interrupt-parent = <&plic>;
+ interrupts = <42 43 44 45>;
+ #pwm-cells = <2>;
+ sifive,approx-period = <1000000>;
+};
--
2.7.4
