[PATCH v3] soc: mediatek: add a fixed wait for SRAM stable

[sean.wang]

From: Sean Wang <sean.w...@mediatek.com>

MT7622_POWER_DOMAIN_WB doesn't send an ACK when its managed SRAM becomes
stable, which is not like the behavior the other power domains should
have. Therefore, it's necessary for such a power domain to have a fixed
and well-predefined duration to wait until its managed SRAM can be allowed
to access by all functions running on the top.

v1 -> v2:
 - use MTK_SCPD_FWAIT_SRAM flag as an indication requiring force waiting.

v2 -> v3:
 - change the order for condition judgment with we check an existence of
   the MTK_SCPD_FWAIT_SRAM first to get rid of any oversight on negative
   condition.

Signed-off-by: Sean Wang <sean.w...@mediatek.com>
Cc: Matthias Brugger <matthias....@gmail.com>
Cc: Ulf Hansson <ulf.hans...@linaro.org>
Cc: Weiyi Lu <weiyi...@mediatek.com>
---
 drivers/soc/mediatek/mtk-scpsys.c | 23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-scpsys.c 
b/drivers/soc/mediatek/mtk-scpsys.c
index b1b45e4..2080c8f 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -32,6 +32,7 @@
 #define MTK_POLL_TIMEOUT    (jiffies_to_usecs(HZ))
 
 #define MTK_SCPD_ACTIVE_WAKEUP         BIT(0)
+#define MTK_SCPD_FWAIT_SRAM            BIT(1)
 #define MTK_SCPD_CAPS(_scpd, _x)       ((_scpd)->data->caps & (_x))
 
 #define SPM_VDE_PWR_CON                        0x0210
@@ -237,11 +238,21 @@ static int scpsys_power_on(struct generic_pm_domain 
*genpd)
        val &= ~scpd->data->sram_pdn_bits;
        writel(val, ctl_addr);
 
-       /* wait until SRAM_PDN_ACK all 0 */
-       ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == 0,
-                                MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
-       if (ret < 0)
-               goto err_pwr_ack;
+       /* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
+       if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
+               /*
+                * Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
+                * MT7622_POWER_DOMAIN_WB and thus just a trivial setup is
+                * applied here.
+                */
+               usleep_range(12000, 12100);
+
+       } else {
+               ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == 0,
+                                        MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+               if (ret < 0)
+                       goto err_pwr_ack;
+       };
 
        if (scpd->data->bus_prot_mask) {
                ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
@@ -785,7 +796,7 @@ static const struct scp_domain_data 
scp_domain_data_mt7622[] = {
                .sram_pdn_ack_bits = 0,
                .clk_id = {CLK_NONE},
                .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
-               .caps = MTK_SCPD_ACTIVE_WAKEUP,
+               .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
        },
 };
 
-- 
2.7.4