Quoting Ryder Lee (2018-04-17 05:30:27)
> The hdmitx_dig_cts clock signal is not a child of clk26m,
> and the actual output of the PLL block is derived from
> the tvdpll via a configurable PLL post-divider.
>
> It is used as the PLL reference input to the HDMI PHY module.
>
> Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
> Signed-off-by: Chunhui Dai <[email protected]>
> Signed-off-by: Ryder Lee <[email protected]>
> ---Applied to clk-next
