On Mon, 4 Jun 2018 18:46:56 +0300 Tudor Ambarus <[email protected]> wrote:
> Hi, Peter, > > On 05/28/2018 01:10 PM, Peter Rosin wrote: > > [cut] > > > So, I think I want either > > > > A) the NAND controller to use master 1 DMAC0/IF0 (i.e. slave 8 DDR2 port 2) > > and > > the LCDC to use master 9 (i.e. slave 9 DDR2 Port 3) > > > > or > > > > B) the NAND controller to use master 2 DMAC0/IF1 (i.e. slave 7 DDR2 port 1, > > and > > possibly slave 9 DDR2 port 3 (if my previous findings are relevant) and > > the > > LCDC to use master 8 (i.e. slave 8 DDR2 Port 2) > > My understanding is that "Table 14-3. Master to Slave Access" describes > what connections are allowed between the masters and slaves, while the > PRxSy registers just set the priorities. What happens when you assign > the highest priority to a master to slave connection that is not > allowed? Probably it is ignored, but I'll check with the hardware team. > So I expect that the NAND controller can not use DDR2 port 3 regardless > of the priority set. > > [cut] > > > So, output is as expected and I believe that the patch makes the NAND DMA > > accesses use master 2 DMAC0/IF1 and are thus forced to use slave 7 DDR2 > > Port 1 > > (and possibly 9). The LCDC is using slave 8 DDR2 Port 2. So there should be > > no > > slave conflict? > > > > But the on-screen crap remains during NAND accesses. > > No conflict, but you missed to dispatch the load on the LCDC DMA > masters, if I understood correctly. > > So, I think we want to test the following: > - NAND controller to use DMAC0/IF1 (slave 7 DDR2 port 1) As I explained in one of my previous email, it's not that easy to set up, because the SRAM is connected to IF0, and we're using DMA memcpy here. Also, I don't see how it could solve Peter's problem if, even when he switches to LCDC master 9 for the primary overlay, he still keeps experiencing FIFO underruns. > - LCDC to use master 8 (slave 8 DDR2 Port 2) and master 9 (slave 9 DDR2 > Port 3). Except that only works if you have several overlays activated, which AFAIR, is not the case in Peter's setup.
