On Fri, May 25, 2018 at 02:42:09PM -0700, Tony Luck wrote:
> Currently we just check the "CAPID0" register to see whether the CPU
> can recover from machine checks.
>
> But there are also some special SKUs which do not have all advanced
> RAS features, but do enable machine check recovery for use with NVDIMMs.
>
> Add a check for any of bits {8:5} in the "CAPID5" register (each
> reports some NVDIMM mode available, if any of them are set, then
> the system supports memory machine check recovery).
>
> Cc: [email protected] # 4.9
> Signed-off-by: Tony Luck <[email protected]>
> ---
Has this stalled somewhere? I'd like to see this one go into the
4.18 merge because it unbreaks some real hardware.
Parts 1 & 2 are nice-to-have, but they just make for better error
messages so aren't as critical.
> arch/x86/kernel/quirks.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
> index 697a4ce04308..736348ead421 100644
> --- a/arch/x86/kernel/quirks.c
> +++ b/arch/x86/kernel/quirks.c
> @@ -645,12 +645,19 @@ static void quirk_intel_brickland_xeon_ras_cap(struct
> pci_dev *pdev)
> /* Skylake */
> static void quirk_intel_purley_xeon_ras_cap(struct pci_dev *pdev)
> {
> - u32 capid0;
> + u32 capid0, capid5;
>
> pci_read_config_dword(pdev, 0x84, &capid0);
> + pci_read_config_dword(pdev, 0x98, &capid5);
>
> - if ((capid0 & 0xc0) == 0xc0)
> + /*
> + * CAPID0{7:6} indicate whether this is an advanced RAS SKU
> + * CAPID5{8:5} indicate that various NVDIMM usage modes are
> + * enabled, so memory machine check recovery is also enabled.
> + */
> + if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0))
> static_branch_inc(&mcsafe_key);
> +
> }
> DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0ec3,
> quirk_intel_brickland_xeon_ras_cap);
> DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0,
> quirk_intel_brickland_xeon_ras_cap);
> --
> 2.17.0
>
