On 07.06.2018 09:56, Uwe Kleine-König wrote: > On Fri, Apr 20, 2018 at 02:44:07PM +0200, Stefan Agner wrote: >> To reset the UART the SRST needs be cleared (low active). According >> to the documentation the bit will remain active for 4 module clocks >> until it is cleared (set to 1). >> >> Hence the real register need to be read in case the cached register >> indicates that the SRST bit is zero. >> >> This bug lead to wrong baudrate because the baud rate register got >> restored before reset completed in imx_flush_buffer. >> >> Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and >> UFCR") >> Signed-off-by: Stefan Agner <ste...@agner.ch> >> Reviewed-by: Fabio Estevam <fabio.este...@nxp.com> >> Reviewed-by: Uwe Kleine-König <u.kleine-koe...@pengutronix.de> > > For the record, there is a customer of mine who reports that this commit > breaks rs485 communication on i.MX25 because RTS stops to toggle as > intended. > > (Some details: uart3, fsl,uart-has-rtscts, fsl,dte-mode, > linux,rs485-enabled-at-boot-time, native RTS.) > > I didn't debug this yet.
I have seen your patch today "serial: imx: fix comment about UCR2_SRST and its handling for shadowing" so I assume you looked into this issue? Was it related to that change? -- Stefan