On Mon, Jun 11, 2018 at 07:35:21AM -0400, Neil Horman wrote: > On Fri, Jun 08, 2018 at 07:09:42PM +0200, Jarkko Sakkinen wrote: > > From: Sean Christopherson <[email protected]> > > > > Intel(R) SGX is a set of CPU instructions that can be used by applications > > to set aside private regions of code and data. The code outside the enclave > > is disallowed to access the memory inside the enclave by the CPU access > > control. > > > > This commit adds the check for SGX to arch/x86 and a new config option, > > INTEL_SGX_CORE. Exposes a boolean variable 'sgx_enabled' to query whether > > or not the SGX support is available. > > > > Signed-off-by: Sean Christopherson <[email protected]> > > Reviewed-by: Jarkko Sakkinen <[email protected]> > > Tested-by: Jarkko Sakkinen <[email protected]> > > Signed-off-by: Jarkko Sakkinen <[email protected]> > > --- > > arch/x86/Kconfig | 19 ++++++++++++ > > arch/x86/include/asm/sgx.h | 25 ++++++++++++++++ > > arch/x86/include/asm/sgx_pr.h | 20 +++++++++++++ > > arch/x86/kernel/cpu/Makefile | 1 + > > arch/x86/kernel/cpu/intel_sgx.c | 53 +++++++++++++++++++++++++++++++++ > > 5 files changed, 118 insertions(+) > > create mode 100644 arch/x86/include/asm/sgx.h > > create mode 100644 arch/x86/include/asm/sgx_pr.h > > create mode 100644 arch/x86/kernel/cpu/intel_sgx.c > > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > > index c07f492b871a..42015d5366ef 100644 > > --- a/arch/x86/Kconfig > > +++ b/arch/x86/Kconfig > > @@ -1925,6 +1925,25 @@ config X86_INTEL_MEMORY_PROTECTION_KEYS > > > > If unsure, say y. > > > > +config INTEL_SGX_CORE > > + prompt "Intel SGX core functionality" > > + def_bool n > > + depends on X86_64 && CPU_SUP_INTEL > > + help > > + Intel Software Guard eXtensions (SGX) is a set of CPU instructions > > + that allows ring 3 applications to create enclaves; private regions > > + of memory that are protected, by hardware, from unauthorized access > > + and/or modification. > > + > > + This option enables kernel recognition of SGX, high-level management > > + of the Enclave Page Cache (EPC), tracking and writing of SGX Launch > > + Enclave Hash MSRs, and allows for virtualization of SGX via KVM. By > > + iteslf, this option does not provide SGX support to userspace. > > + > > + For details, see Documentation/x86/intel_sgx.rst > > + > > + If unsure, say N. > > + > > config EFI > > bool "EFI runtime service support" > > depends on ACPI > > diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h > > new file mode 100644 > > index 000000000000..fa3e6e0eb8af > > --- /dev/null > > +++ b/arch/x86/include/asm/sgx.h > > @@ -0,0 +1,25 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > > +// Copyright(c) 2016-18 Intel Corporation. > > +// > > +// Authors: > > +// > > +// Jarkko Sakkinen <[email protected]> > > +// Suresh Siddha <[email protected]> > > +// Sean Christopherson <[email protected]> > > + > > +#ifndef _ASM_X86_SGX_H > > +#define _ASM_X86_SGX_H > > + > > +#include <linux/types.h> > > + > > +#define SGX_CPUID 0x12 > > + > Agree with Dave, this can just be remoed and you can use the feature macro > from > cpuid.h instead > > Neil
Will do, thanks. /Jarkko
