On Wed 23 May 17:35 PDT 2018, Rishabh Bhatnagar wrote: > Documentation for last level cache controller device tree bindings, > client bindings usage examples. > > Signed-off-by: Channagoud Kadabi <[email protected]> > Signed-off-by: Rishabh Bhatnagar <[email protected]> > Reviewed-by: Evan Green <[email protected]> > Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]> Regards, Bjorn > --- > .../devicetree/bindings/arm/msm/qcom,llcc.txt | 26 > ++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > > diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > new file mode 100644 > index 0000000..5e85749 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > @@ -0,0 +1,26 @@ > +== Introduction== > + > +LLCC (Last Level Cache Controller) provides last level of cache memory in > SOC, > +that can be shared by multiple clients. Clients here are different cores in > the > +SOC, the idea is to minimize the local caches at the clients and migrate to > +common pool of memory. Cache memory is divided into partitions called slices > +which are assigned to clients. Clients can query the slice details, activate > +and deactivate them. > + > +Properties: > +- compatible: > + Usage: required > + Value type: <string> > + Definition: must be "qcom,sdm845-llcc" > + > +- reg: > + Usage: required > + Value Type: <prop-encoded-array> > + Definition: Start address and the the size of the register region. > + > +Example: > + > + cache-controller@1100000 { > + compatible = "qcom,sdm845-llcc"; > + reg = <0x1100000 0x250000>; > + }; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
