Add missing insn suffixes and use rmwcc.h just like was (more or less) recently done for bitops.h as well.
Signed-off-by: Jan Beulich <jbeul...@suse.com> --- arch/x86/include/asm/sync_bitops.h | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) --- 4.18-rc2/arch/x86/include/asm/sync_bitops.h +++ 4.18-rc2-x86-sync-bitops-insn-suffixes/arch/x86/include/asm/sync_bitops.h @@ -14,6 +14,8 @@ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). */ +#include <asm/rmwcc.h> + #define ADDR (*(volatile long *)addr) /** @@ -29,7 +31,7 @@ */ static inline void sync_set_bit(long nr, volatile unsigned long *addr) { - asm volatile("lock; bts %1,%0" + asm volatile("lock; " __ASM_SIZE(bts) " %1,%0" : "+m" (ADDR) : "Ir" (nr) : "memory"); @@ -47,7 +49,7 @@ static inline void sync_set_bit(long nr, */ static inline void sync_clear_bit(long nr, volatile unsigned long *addr) { - asm volatile("lock; btr %1,%0" + asm volatile("lock; " __ASM_SIZE(btr) " %1,%0" : "+m" (ADDR) : "Ir" (nr) : "memory"); @@ -64,7 +66,7 @@ static inline void sync_clear_bit(long n */ static inline void sync_change_bit(long nr, volatile unsigned long *addr) { - asm volatile("lock; btc %1,%0" + asm volatile("lock; " __ASM_SIZE(btc) " %1,%0" : "+m" (ADDR) : "Ir" (nr) : "memory"); @@ -78,14 +80,10 @@ static inline void sync_change_bit(long * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ -static inline int sync_test_and_set_bit(long nr, volatile unsigned long *addr) +static inline bool sync_test_and_set_bit(long nr, volatile unsigned long *addr) { - unsigned char oldbit; - - asm volatile("lock; bts %2,%1\n\tsetc %0" - : "=qm" (oldbit), "+m" (ADDR) - : "Ir" (nr) : "memory"); - return oldbit; + GEN_BINARY_RMWcc("lock; " __ASM_SIZE(bts), + *addr, "Ir", nr, "%0", c); } /** @@ -98,12 +96,8 @@ static inline int sync_test_and_set_bit( */ static inline int sync_test_and_clear_bit(long nr, volatile unsigned long *addr) { - unsigned char oldbit; - - asm volatile("lock; btr %2,%1\n\tsetc %0" - : "=qm" (oldbit), "+m" (ADDR) - : "Ir" (nr) : "memory"); - return oldbit; + GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btr), + *addr, "Ir", nr, "%0", c); } /** @@ -116,12 +110,8 @@ static inline int sync_test_and_clear_bi */ static inline int sync_test_and_change_bit(long nr, volatile unsigned long *addr) { - unsigned char oldbit; - - asm volatile("lock; btc %2,%1\n\tsetc %0" - : "=qm" (oldbit), "+m" (ADDR) - : "Ir" (nr) : "memory"); - return oldbit; + GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btc), + *addr, "Ir", nr, "%0", c); } #define sync_test_bit(nr, addr) test_bit(nr, addr)