On Fri, 3 Aug 2018 18:54:03 +0900 <hayashi.kunih...@socionext.com> wrote:
> Add a driver for PHY interface built into USB3 controller
> implemented in UniPhier SoCs.
> This driver supports High-Speed PHY and Super-Speed PHY.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunih...@socionext.com>
> Signed-off-by: Motoya Tanigawa <tanigawa.mot...@socionext.com>
> Signed-off-by: Masami Hiramatsu <masami.hirama...@linaro.org>
> ---
> drivers/phy/Kconfig | 1 +
> drivers/phy/Makefile | 1 +
> drivers/phy/socionext/Kconfig | 12 +
> drivers/phy/socionext/Makefile | 6 +
> drivers/phy/socionext/phy-uniphier-usb3hs.c | 423
> ++++++++++++++++++++++++++++
> drivers/phy/socionext/phy-uniphier-usb3ss.c | 350 +++++++++++++++++++++++
> 6 files changed, 793 insertions(+)
> create mode 100644 drivers/phy/socionext/Kconfig
> create mode 100644 drivers/phy/socionext/Makefile
> create mode 100644 drivers/phy/socionext/phy-uniphier-usb3hs.c
> create mode 100644 drivers/phy/socionext/phy-uniphier-usb3ss.c
[snip]
> +static void uniphier_u3ssphy_testio_write(struct uniphier_u3ssphy_priv *priv,
> + u32 data)
> +{
> + /* need to read TESTO twice after accessing TESTI */
> + writel(data, priv->base + SSPHY_TESTI);
> + readl(priv->base + SSPHY_TESTI);
> + readl(priv->base + SSPHY_TESTI);
I made a mistake here. The comment and the code are inconsistent.
I'll fix it next.
Thanks,
---
Best Regards,
Kunihiko Hayashi
