On Fri, Sep 21, 2018 at 06:01:49PM -0400, ryang wrote: > The current behavior is that clk_round_rate would return the same clock > rate passed to it for valid PLL configurations. This change will return > the exact rate the PLL will provide in accordance with clk API. > > Signed-off-by: ryang <[email protected]> > --- > drivers/clk/tegra/clk-pll.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-)
With Peter's comment addressed: Acked-by: Thierry Reding <[email protected]>
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