Quoting Icenowy Zheng (2018-10-18 00:07:29) > In the user manual of A64 SoC, the bit 22 and 23 of pll-mipi control > register is called "LDO{1,2}_EN", and according to the BSP source code > from Allwinner , the LDOs are enabled during the clock's enabling > process. > > The clock failed to generate output if the two LDOs are not enabled. > > Add the two bits to the clock's gate bits, so that the LDOs are enabled > when the PLL is enabled. > > Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") > Signed-off-by: Icenowy Zheng <icen...@aosc.io> > ---
Looks OK to me from not knowing anything about this driver. Shall I pick directly into clk-next for next release?