+ Chandan from Display Port team,
On 10/30/2018 10:03 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-29 23:01:44)
On 10/30/2018 12:13 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-28 03:34:55)
On 2018-10-19 16:04, Taniya Das wrote:
On 10/10/2018 2:04 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-09 06:57:47)
diff --git a/drivers/clk/qcom/dispcc-sdm845.c
b/drivers/clk/qcom/dispcc-sdm845.c
index 0cc4909..6d3136a 100644
--- a/drivers/clk/qcom/dispcc-sdm845.c
+++ b/drivers/clk/qcom/dispcc-sdm845.c
+ },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
+ F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
Are these in kHz? They really look like it and that's bad. Why do we
need them at all? Just to make sure the display driver picks these
exact
frequencies? It seems like we could just pass whatever number comes in
up to the parent and see what it can do.
Let me check back the reason we had to make this change.
We will need this flag since we reset/power-down the PLL every time we
disconnect/connect the DP cable or during suspend/resume. Only with this
flag, the calls to the PLL driver are properly called.
What does this mean? I wanted to know about the weird frequencies listed
above, and why it can't be done without a frequency table and direct
rates passed up to the parent.
OOps, my bad :(.
We added these changes to handle higher clock rates. These rates when
greater than 4.3Ghz cannot be represented in 32bit variables. For DP, we
already have 5.4G and 8.1GHz freq for VCO clock. We will need these Khz
freq list in clock driver.
Let me check if they can do something like the byte/pixel clocks of
display.
Well then we really should just throw away the freq table here and have
rcg ops that pass the frequency up to the display PLL. Also, those
numbers look like gigabits per second (Gbit/s) for the DP spec which
isn't exactly the same as a clk frequency. What frequency does the PLL
run at for these various DP link speeds?
Could you please help with the above query from Stephen?
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