Commit-ID: 2e94061096c5c3aa6c3fe3ec2bec176c1f9c1b07 Gitweb: https://git.kernel.org/tip/2e94061096c5c3aa6c3fe3ec2bec176c1f9c1b07 Author: Borislav Petkov <b...@suse.de> AuthorDate: Thu, 12 Apr 2018 13:11:36 +0200 Committer: Borislav Petkov <b...@suse.de> CommitDate: Mon, 19 Nov 2018 21:55:32 +0100
x86/TSC: Use RDTSCP Currently, the kernel uses [LM]FENCE; RDTSC in the timekeeping code, to guarantee monotonicity of time where the *FENCE is selected based on vendor. Replace that sequence with RDTSCP which is faster or on-par and gives the same guarantees. A microbenchmark on Intel shows that the change is on-par. On AMD, the change is either on-par with the current LFENCE-prefixed RDTSC and some are slightly better with RDTSCP. The comparison is done with the LFENCE-prefixed RDTSC (and not with the MFENCE-prefixed one, as one would normally expect) because all modern AMD families make LFENCE serializing and thus avoid the heavy MFENCE by effectively enabling X86_FEATURE_LFENCE_RDTSC. Co-developed-by: Thomas Gleixner <t...@linutronix.de> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Signed-off-by: Borislav Petkov <b...@suse.de> Reviewed-by: Tom Lendacky <thomas.lenda...@amd.com> Acked-by: Andy Lutomirski <l...@kernel.org> Cc: "H. Peter Anvin" <h...@zytor.com> Cc: John Stultz <john.stu...@linaro.org> Cc: x...@kernel.org Link: https://lkml.kernel.org/r/20181119184556.11479-1...@alien8.de --- arch/x86/include/asm/msr.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 91e4cf189914..f00f2b61d326 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -217,6 +217,8 @@ static __always_inline unsigned long long rdtsc(void) */ static __always_inline unsigned long long rdtsc_ordered(void) { + DECLARE_ARGS(val, low, high); + /* * The RDTSC instruction is not ordered relative to memory * access. The Intel SDM and the AMD APM are both vague on this @@ -227,9 +229,18 @@ static __always_inline unsigned long long rdtsc_ordered(void) * ordering guarantees as reading from a global memory location * that some other imaginary CPU is updating continuously with a * time stamp. + * + * Thus, use the preferred barrier on the respective CPU, aiming for + * RDTSCP as the default. */ - barrier_nospec(); - return rdtsc(); + asm volatile(ALTERNATIVE_2("mfence; rdtsc", + "lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC, + "rdtscp", X86_FEATURE_RDTSCP) + : EAX_EDX_RET(val, low, high) + /* RDTSCP clobbers ECX with MSR_TSC_AUX. */ + :: "ecx"); + + return EAX_EDX_VAL(val, low, high); } static inline unsigned long long native_read_pmc(int counter)
