On Fri 26 Oct 10:35 PDT 2018, Evan Green wrote:
> Add the second lane registers for the USB PHY, now that the
> QMP phy bindings have been updated. This way the driver can stop
> reaching beyond its register region to get at the second lane.
>
> Signed-off-by: Evan Green <evgr...@chromium.org>
> Reviewed-by: Douglas Anderson <diand...@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.anders...@linaro.org>
Regards,
Bjorn
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
> - Removed erroneous fixup for USB UniPro PHY, which is not dual lane (Doug)
>
> Changes in v2: None
>
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 9c72edb678ec..ff2db36ec4fa 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1188,10 +1188,12 @@
> <&gcc GCC_USB3_PHY_PRIM_BCR>;
> reset-names = "phy", "common";
>
> - usb_1_ssphy: lane@88e9200 {
> + usb_1_ssphy: lanes@88e9200 {
> reg = <0x88e9200 0x128>,
> <0x88e9400 0x200>,
> <0x88e9c00 0x218>,
> + <0x88e9600 0x128>,
> + <0x88e9800 0x200>,
> <0x88e9a00 0x100>;
> #phy-cells = <0>;
> clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> --
> 2.16.4
>
