Quoting Janek Kotas (2018-11-30 00:52:16) > > We have a single register in a fixed location which contains > the frequency of the main system clock. > This allows us to use the same image in emulation, FPGA > and simulation without any changes. > We usually don’t use a full bootloader, just a simple wrapper, > which initializes the necessary stuff and jumps to the kernel. > > > So the hardware team has decided to throw a frequency register in there? > Alright! Does that fixed rate clk generate its fixed rate from some > other clk? I’m curious if this fixed rate clk has a parent source. > > > It depends, in simulation and emulation we can just generate > a clock source with a given frequency. > On FPGA it’s usually an external oscillator, sometimes a fixed PLL. > The driver is not intended to be used in full, complex SoCs.
Ok, sounds like it isn't worth modeling this then. > > > It would also be good to make sure that any clks registered from this > driver can't be populated from regions of memory like DDR. Can you > confirm? I think it will fail, but it would be worth checking > Please try this. > Yes I'd prefer a platform driver unless there's some reason it can't be > done. We may need to have both in case this needs to be populated very > early, but if that isn’t the case then just a platform driver for now. > > > I played with it a bit, and it and it looks like I need both. > We use this clock source with some of our components, > and for some of them the platform driver was initialized too late. > Ok. So do both then.
