Hi Boris,
> -----Original Message-----
> From: Boris Brezillon [mailto:[email protected]]
> Sent: Tuesday, November 20, 2018 9:55 PM
> To: Naga Sureshkumar Relli <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; Michal Simek
> <[email protected]>; [email protected]; [email protected];
> linux-
> [email protected]; [email protected]
> Subject: Re: [LINUX PATCH v12 3/3] mtd: rawnand: arasan: Add support for
> Arasan
> NAND Flash Controller
>
> On Fri, 9 Nov 2018 10:30:41 +0530
> Naga Sureshkumar Relli <[email protected]> wrote:
>
> > +static int anfc_setup_data_interface(struct nand_chip *chip, int csline,
> > + const struct nand_data_interface *conf) {
> > + struct anfc_nand_controller *nfc = to_anfc(chip->controller);
> > + struct anfc_nand_chip *achip = to_anfc_nand(chip);
> > + int err;
> > + const struct nand_sdr_timings *sdr;
> > + u32 inftimeval;
> > + bool change_sdr_clk = false;
> > +
> > + if (csline == NAND_DATA_IFACE_CHECK_ONLY)
> > + return 0;
> > +
> > + /*
> > + * If the controller is already in the same mode as flash device
> > + * then no need to change the timing mode again.
> > + */
> > + sdr = nand_get_sdr_timings(conf);
> > + if (IS_ERR(sdr))
> > + return PTR_ERR(sdr);
> > +
> > + if (sdr->mode < 0)
> > + return -ENOTSUPP;
> > +
> > + inftimeval = sdr->mode & 7;
> > + if (sdr->mode >= 2 && sdr->mode <= 5)
> > + change_sdr_clk = true;
> > + /*
> > + * SDR timing modes 2-5 will not work for the arasan nand when
> > + * freq > 90 MHz, so reduce the freq in SDR modes 2-5 to < 90Mhz
>
> What's the freq for mode 0 and 1?
It is 100MHz in SDR mode 0 and 1.
>
> > + */
> > + if (change_sdr_clk) {
> > + clk_disable_unprepare(nfc->clk_sys);
> > + err = clk_set_rate(nfc->clk_sys, SDR_MODE_DEFLT_FREQ);
>
> You should not change the clk rate here. It should be done when the chip is
> selected, so that,
> if you ever have 2 different chips connected to the same controller, you can
> adapt the rate
> when they are accessed.
Ok, got it. I will update.
>
> > + if (err) {
> > + dev_err(nfc->dev, "Can't set the clock rate\n");
> > + return err;
> > + }
> > + err = clk_prepare_enable(nfc->clk_sys);
> > + if (err) {
> > + dev_err(nfc->dev, "Unable to enable sys clock.\n");
> > + clk_disable_unprepare(nfc->clk_sys);
> > + return err;
> > + }
> > + }
> > + achip->inftimeval = inftimeval;
> > +
> > + return 0;
> > +}
> > +
> > +static int anfc_nand_attach_chip(struct nand_chip *chip) {
> > + struct mtd_info *mtd = nand_to_mtd(chip);
> > + struct anfc_nand_chip *achip = to_anfc_nand(chip);
> > + u32 ret;
> > +
> > + if (mtd->writesize <= SZ_512)
> > + achip->spare_caddr_cycles = 1;
> > + else
> > + achip->spare_caddr_cycles = 2;
> > +
> > + chip->ecc.calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL);
> > + chip->ecc.code_buf = kmalloc(mtd->oobsize, GFP_KERNEL);
>
> Those bufs are allocated but never freed (memleak). Also, are you sure you
> really need them.
These bufs are freed in nand_release(), which is calling from anfc_remove().
And chip->ecc.code_buf, is used in anfc_read_page_hwecc().
What we are doing here is, extract ECC code from OOB and place it in
ecv.code_buf, and passing this info to nand_check_ecc_chunk(buf,
chip->ecc.size, &ecc_code[i], eccbytes, NULL, 0,chip->ecc.strength).
i.e. just to store ECC code from OOB area.
And chip->ecc.calc_buf is no where used in the driver, I will remove it.
Thanks,
Naga Sureshkumar Relli.
