cadence-quadspi controller allows upto eight bytes of data to be transferred
in software Triggered Instruction generator (STIG) mode of operation. Lower
4 bytes are written through writedatalower and upper 4 bytes by
writedataupper register.

This patch allows all the 8 bytes to be written.

Signed-off-by: Purna Chandra Mandal <purna.chandra.man...@intel.com>
---

 drivers/mtd/spi-nor/cadence-quadspi.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c 
b/drivers/mtd/spi-nor/cadence-quadspi.c
index 04cedd3a2bf6..990934387fea 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -420,7 +420,7 @@ static int cqspi_command_write(struct spi_nor *nor, const 
u8 opcode,
        unsigned int data;
        int ret;
 
-       if (n_tx > 4 || (n_tx && !txbuf)) {
+       if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
                dev_err(nor->dev,
                        "Invalid input argument, cmdlen %d txbuf 0x%p\n",
                        n_tx, txbuf);
@@ -435,8 +435,13 @@ static int cqspi_command_write(struct spi_nor *nor, const 
u8 opcode,
                data = 0;
                memcpy(&data, txbuf, n_tx);
                writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
-       }
 
+               if (n_tx > 4) {
+                       data = 0;
+                       memcpy(&data, txbuf + 4, n_tx - 4);
+                       writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
+               }
+       }
        ret = cqspi_exec_flash_cmd(cqspi, reg);
        return ret;
 }
-- 
2.13.0

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