On Wed, 2 Jan 2019 12:57:52 -0800, Sowjanya Komatineni wrote: > Add pinctrl for 3V3 and 1V8 pad drive strength configuration for > Tegra210 sdmmc which has pad configuration registers in the pinmux > reigster domain. > Pad drive strengths for Tegra186 and Later are > part of SDMMC device node itself. > > Signed-off-by: Sowjanya Komatineni <skomatin...@nvidia.com> > --- > Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) >
Reviewed-by: Rob Herring <r...@kernel.org>
