On Fri, Jan 11, 2019 at 06:11:04PM +0000, James Morse wrote:
> After I sent this it occurred to me the core can't know about errors in the L3
> cache (if there is one) or the memory-controller. These may have edac/ras
> abilities, but they are selected by the soc integrator, so could be per soc.
> This goes against Boris's no-per-functional-unit edac drivers. If we had to
> pick
> one out of that set, I think the memory-controller is most useful as DRAM is
> the
> most likely to be affected by errors.
We have similar "designs" already :)
Memory controller driver drivers/edac/fsl_ddr_edac.c gets linked together with:
mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o
obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o
obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
